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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/21/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.all;

ENTITY par2ser_8bit IS
	PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
			reset			: IN  STD_LOGIC;	-- Reset input
			enable			: IN  STD_LOGIC;	-- Enable			
			input			: IN  STD_LOGIC_VECTOR (7 DOWNTO 0);	-- Input
			n_bytes			: IN  STD_LOGIC_VECTOR (15 DOWNTO 0);	-- Expected N bytes
			stop_signal		: INOUT STD_LOGIC;
      		q	 			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 	-- Output
			);
END par2ser_8bit;

ARCHITECTURE behav OF par2ser_8bit IS
	SIGNAL mux_select : STD_LOGIC;
	SIGNAL counter: STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
	PROCESS (clock, reset, enable, input)
	BEGIN
		IF reset = '1' OR input = x"00" THEN
	 	    mux_select <= '0';
			counter <= x"0000";
			q <= "0000";	
			stop_signal <= '0';
		ELSIF enable = '1' AND stop_signal = '0' THEN
			IF (clock'event AND clock = '1') THEN
				IF mux_select = '0' THEN
					q <= input(3 DOWNTO 0);
					mux_select <= '1';
				ELSIF mux_select = '1' THEN
					q <= input(7 DOWNTO 4);
					counter <= counter + 1;
					mux_select <= '0';
					IF (counter = n_bytes) THEN
						stop_signal <= '1';							
					END IF;
				END IF;
		    END IF;			
		END IF;		
	END PROCESS;
END behav;
